DC-to-DC power converters are used in a wide variety of products. They are key in the areas of renewable energy resources (solar cells), products requiring alternative voltages (liquid crystal displays), remote powered communications networks (remote cell phone repeater stations), and battery powered devices such as cellular phones and laptop computers.
DC-to-DC converters, battery chargers, audio amplifiers, and power regulators require a way of sensing an output current. Feedback based on the output current can regulate sourcing circuitry to maintain a steady output characteristic and protect output circuitry from an overload current.
Typically, a resistor has been used inline with an output node and configured to develop a sensing voltage across it. Sensed current or voltage quantities may be compared with internal reference sources and combined within digital circuitry to provide controlling signals to output drive devices. A comparison and feedback path allows output current and voltage to be maintained across varying environmental conditions such as characteristics of load demand, temperature, source voltage, and implementation technologies. A drawback of this approach to circuit characteristic sensing is the significant amount of current required, as much as 1 amp in certain implementations, which reduces the efficiency of the converter or regulating device proportionately. Furthermore, a precision external resistor is expensive and difficult to integrate.
With regard to FIG. 1, exemplifying a prior art device, a feedback signal is formed, within a DC-to-DC converter 100, through comparing and combining sensed output characteristics with reference sources. A first modifying feedback signal is produced at an output of a first comparator 130. A first input node of the first comparator 130 is supplied with a first sense voltage from an output node 125 of an NMOS drive transistor 120. A second input node of the first comparator 130 is supplied with a voltage output from a first voltage reference source 132. A second modifying signal is produced at an output of a second comparator 136 supplied with an output voltage characteristic from a voltage divider node 141 and a voltage output from a second voltage reference source 148. The two modifying signals are combined within a digital circuit 134 with the combined signals supplied as feedback to a driver 138. An output 139 of the driver 138 produces a drive level control signal. The drive level control signal produces a regulated drive level at the output node 125 of the drive transistor 120.
In further regard to FIG. 1, an internal or external sense resistor 105 conducts a sense current 115 coming from the output node 125. The sense current 115 flowing through the external sense resistor 105, creates the first sense voltage which is input to the first comparator 130. The voltage divider node 141 connects a first internal resistor 140 to a second internal resistor 142 forming a series combination. An input to the first internal resistor 140 is connected to a converter output node 144 and an output of the second internal resistor 142 is connected to a ground 160. A second input of the second comparator 136 is from an output of the second voltage reference source 148. The voltage output from the voltage divider node 141 is a second sense voltage measuring a characteristic of a voltage output from the converter output node 144. The second sense voltage is compared within the second comparator 136 with a voltage output from the reference voltage source 148.
Sourcing and biasing devices connect to the DC-to-DC converter 100 for operation. A battery 150 producing a source voltage Vin, is a power source of the externally sensed DC-to-DC converter 100. The battery 150 is connected to an input node 152 and to an input of an inductor 153. An output of the inductor 153 connects to a sensing node 154. An electrical rectifying device, a diode 156, is connected at an anode to the sensing node 154 and at a cathode to the converter output node 144. The diode 156 provides an electrical isolation of the sensing node 154 from any occurrence of a voltage at the converter output node 144 exceeding a potential greater than a diode device threshold below the sensing node 154. An electrical charge storage device, a capacitor 158, is connected at an input to the converter output node 144 and at an output to ground 160.
With regard to FIG. 2, also a prior art device, a current mirror sensed DC-to-DC converter 200 contains an internal sense resistor 205 connected at an input to the sensing node 154 and at an output to a first input of an NMOS current mirror transistor 215. A sense voltage of about 100 millivolts across sense resistor 205 and a mirror current of about 100 microamperes are targeted. A value for the internal sense resistor 205 is typically 1 kilohms. The current mirror transistor 215 is connected at an output to ground 160 and is connected at a second input, or gate input, to the output 139 of the driver 138. The series connection of current mirror transistor 215 with the internal sense resistor 205 forms a current mirror. An input to the internal sense resistor 205 is connected in parallel to a first input of the drive transistor 120 and a control input to the current mirror transistor 215 is connected in parallel to a control input or second input of the drive transistor 120. The configuration of the internal sense resistor 205 and the current mirror transistor 215 in parallel with drive transistor 120 allows the current mirror to track the drive characteristics of the current through the drive transistor 120 and to produce a sense current Isense/k 225 through internal sense resistor 205 which reflects the characteristics of Isense 115 at a fraction of the magnitude of current. A first sense voltage, VsenseMn/k, is the voltage at the output of internal sense resistor 205, which is input to a first input of a voltage referenced comparator 210. A second input to the voltage-referenced comparator 210 is the voltage at the sensing node 154. An output of the voltage-referenced comparator 210 is connected to the digital circuit 134.
The value of the internal sense resistor 205 and the current determining device geometries of the current mirror transistor 215 are configured to produce the sense current Isense/k 225 with a magnitude that is a fraction of Isense 115 such that the ratio of Isense/k 225 to Isense 115 is 1-to-k or Isense/k 225 is 1/kth of Isense 115. A value of “k” is chosen to keep the 1/k ratio small and to not detract from power efficiency. A typical value for “k” is about 1000. For example, when a maximum value expected for Isense 115 is 100 milliamperes a 1 kilohm internal sense resistor 205 is chosen to produce an Isense/k 225 of 100 microamperes. Therefore the current mirror formed by the internal sense resistor 205 and the current mirror transistor 215, produces the first sense voltage, VsenseMn/k, using 1/kth the magnitude of current of Isense 115. The current Isense/k 225, conducted through internal sense resistor 205, is a portion of a current that is sourced from the sensing node 154. The current sourced from the sensing node 154 also supplies Isense 115, but Isense/k 225 does not take current from Isense 115. The relatively low current magnitude of Isense/k 225 and the fact that it does not detract from Isense 115 means that a progressive step is gained in efficiency by the current mirror sensed DC-to-DC converter 200 over the externally sensed DC-to-DC converter 100.
A drawback to this technique is that the efficiency is improved as the magnitude of Isense/k 225 becomes smaller. But as Isense/k 225 becomes smaller, accuracy of the first sense voltage VsenseMn/k degrades. Feedback signaling quantities based on VsenseMn/k, such as the drive level control signal at the output 139 of the driver 138, become less useful in producing an accurate drive level control as the circuit is configured for improved efficiency by a reduction in Isense/k 225.
A further drawback of the current mirror sensed DC-to-DC converter 200 is that the common mode voltage range is very wide, on the order of the magnitude of the output voltage. A comparator design for this type of signal characteristic needs a low input common mode voltage range and a high input common mode voltage range ability. For a CMOS implementation technology, the devices implementing the comparator are exposed to source-drain voltages large enough that they are subject to channel length modulation effects. A resultant non-linearity in device performance means an unfavorable device current variation over the operating range. Additional design considerations are thus required, such as current conveyors, which present design challenges and added costs that detract from the benefits gained in the current mirror approach.
What is needed is a power converter with a sensed signal proportional to a target sense current. Ideally, the sensed signal would be detected with no degradation in the efficiency of the converter, based on the linear region of operation of a target drive transistor, and be of a low common mode signal range for ease of comparator design. An ideal sense signal would also be produced without externally or internally added components that are complicated or costly in expense or die area of an implementation technology.